1. Field of the Invention
The present invention relates to a semiconductor memory device in which a stored electric charge is detected as memory information, and more particularly to a memory device in which a soft error due to radioactive rays can be prevented.
2. Description of the Prior Art
Referring to FIG. 1, there is schematically illustrated a conventional dynamic RAM cell in a fragmentary sectional view. A cell area on a semiconductor substrate 1 of a P.sup.- conductivity type is surrounded by an insulator layer 8 and a P.sup.+ layer 9 for field isolation. A charge storage region 6 of an N.sup.+ type and a bit line region 7 of an N.sup.+ type are formed in the cell area. A first gate electrode layer 2 and a second gate electrode layer 3 are formed on a gate insulator layer 4 which is formed on the substrate 1. An insulator layer 5 is interposed for layer insulation between the first and second gate electrode layers 2 and 3.
The first gate electrode 2 is connected to a power source terminal T1, while the second gate electrode 3 is connected to a terminal which leads to a word line. A depletion layer 10 is formed along the boundary of the N.sup.+ storage region 6 in the P.sup.- substrate 1, while a depletion layer 11 is formed along the boundary of the N.sup.+ bit line 7. For clarity, wires and a protective film are omitted in FIG. 1 and the storage region 6 is shown as a doped N.sup.+ layer. As a matter of fact, however, an electric charge is usually accumulated in an N.sup.+ inversion layer which corresponds to the storage region 6 and is induced by applying a positive potential to the first gate electrode 2.
In a conventional cell as shown in FIG. 1, the N.sup.+ bit line 7 is normally maintained at a certain intermediate potential by a sense amplifier (not shown). When a potential is applied to the first gage electrode 3 which acts as a transfer gate, the N.sup.+ bit line 7 communicates with the N.sup.+ storage 6 and then the potential of the bit line 7 is changed depending on a charge accumulated in the storage 6. The potential change of the bit line 7 is sensed and amplified by the sense amplifier, and then the memory cell is refreshed in the same cycle by writing the same memory information.
Since the bit line 7 is formed as an N.sup.+ region or an N.sup.+ inversion region in a conventional memory device, there exists a problem that electrons generated by irradiation of radioactive rays such as .alpha.-rays are collected into the bit line 7 and then cause erroneous operation in the memory device. Further, in case that a P.sup.+ region is formed along the entire interface between the N.sup.+ bit line 7 and the P.sup.- substrate 1 in order to avoid the above problem, a portion of the P.sup.+ region extended into the channel region makes it difficult to stably operate the memory transistor.
Incidentally, a RAM cell with an increased charge storage capacitance is described by V. L. Rideout in IBM Technical Disclosure Bulletin, Vol. 21, No. 9, 1979, pp. 3823-3825.